publications
International journal and conference publications by ACPL
2024
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AcceptedSCIESpDRAM: Efficient In-DRAM Acceleration of Sparse Matrix-Vector MultiplicationIEEE Access, vol.0, num.0, pp.1-1, 2024
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학부생 성과T-FLIP: 어텐션 가중치 기반 지식 증류를 통한 안면 위조 방지 모델 경량화In 2024년도 대한전자공학회 추계학술대회Collaborative research conducted with Chung-Ang University
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AutoCaps-Zero: Searching for Hardware-Efficient Squash Function in Capsule NetworksIn 2024 International Conference on Communications, Computing, Cybersecurity, and Informatics (CCCI)
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OCW: Enhancing Few-Shot Learning with Optimized Class-Weighting MethodsIn 2024 International Conference on Communications, Computing, Cybersecurity, and Informatics (CCCI)
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An Energy-Efficient Hardware Accelerator for On-Device Inference of YOLOXIn 2024 21st International SoC Design Conference (ISOCC)
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BS2: Bit-Serial Architecture Exploiting Weight Bit Sparsity for Efficient Deep Learning AccelerationIn 2024 21st International SoC Design Conference (ISOCC)
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AlphaAccelerator: An Automatic Neural FPGA Accelerator Design Framework Based on GNNsIn 2024 21st International SoC Design Conference (ISOCC)
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SCIEQ-LAtte: An Efficient and Versatile LSTM Model for Quantized Attention-Based Time Series Forecasting in Building Energy ApplicationsIEEE Access, vol.12, pp.69325-69341, 2024
2023
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Optimization of the Modified Gaussian Filter for Mobile GPU Usage in Game WorkloadsIn 2023 International Conference on Communications, Computing, Cybersecurity, and Informatics (CCCI)
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TD-NAAS: Template-Based Differentiable Neural Architecture Accelerator SearchIn 2023 20th International SoC Design Conference (ISOCC)
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학부생 성과
2021
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SCIES-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level SparsityIEEE Transactions on Computers, vol.71, num.6, pp.1291–1304, 2021
2020
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SCIECREMON: Cryptography Embedded on the Convolutional Neural Network AcceleratorIEEE Transactions on Circuits and Systems II: Express Briefs, vol.67, num.12, pp.3337–3341, 2020
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SCIEAn Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart DevicesIEEE Journal of Solid-State Circuits, vol.55, num.10, pp.2691–2702, 2020
2019
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MajorA 47.4 uJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart DevicesIn 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Top-TiereSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN AcceleratorsIn 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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Top-TierA PVT-Robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural NetworksIn 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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Top-TierAn Energy-Efficient Processing-in-Memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAMIn 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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Top-TierNAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural NetworksIn 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)
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SCIEAn Energy-Efficient Deep Convolutional Neural Network Inference Processor with Enhanced Output Stationary Dataflow in 65-nm CMOSIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.28, num.1, pp.87–100, 2019
2018
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Top-TierNID: Processing Binary Convolutional Neural Network in Commodity DRAMIn 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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MajorTrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network TrainingIn 2018 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)
2017
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SCIEEnergy-Efficient Design of Processing Element for Convolutional Neural NetworkIEEE Transactions on Circuits and Systems II: Express Briefs, vol.64, num.11, pp.1332–1336, 2017
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Top-TierA Kernel Decomposition Architecture for Binary-Weight Convolutional Neural NetworksIn 2017 IEEE/ACM 54th Annual Design Automation Conference (DAC)
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MajorSENIN: An Energy-Efficient Sparse Neuromorphic System with On-Chip LearningIn 2017 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)
2016
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Top-TierA 1.42 TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE SystemsIn 2016 IEEE International Solid-State Circuits Conference (ISSCC)
2015
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SCIEA 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery with Hybrid Dithering Using a Time-Dithered Ddelta–Sigma ModulatorIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, num.4, pp.1450–1459, 2015
2014
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MajorTiming Error Masking by Exploiting Operand Value Locality in SIMD ArchitectureIn 2014 IEEE 32nd International Conference on Computer Design (ICCD)Best Paper AwardDOI
2013
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SCIEPowerField: A Probabilistic Approach for Temperature-to-Power Conversion Based on Markov Random Field TheoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.32, num.10, pp.1509–1519, 2013
2012
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Top-TierPowerField: A Transient Temperature-to-Power Technique Based on Markov Random Field TheoryIn 2012 IEEE/ACM 49th Annual Design Automation Conference (DAC)