publications

International journal and conference publications by ACPL

2024

  1. Accepted
    An Energy-Efficient Hardware Accelerator for On-Device Inference of YOLOX
    Kyungmi Kim , Soeun Choi , Eunkyeol Hong , Yoonseo Jang , and Jaehyeong Sim
    In 2024 21st International SoC Design Conference (ISOCC)
  2. Accepted
    BS2: Bit-Serial Architecture Exploiting Weight Bit Sparsity for Efficient Deep Learning Acceleration
    Eunseo Kim , Subean Lee , Chaeyun Kim , HaYoung Lim , Jimin Nam , and Jaehyeong Sim
    In 2024 21st International SoC Design Conference (ISOCC)
  3. Accepted
    AlphaAccelerator: An Automatic Neural FPGA Accelerator Design Framework Based on GNNs
    Jiho Lee , Jieui Kang , Eunjin Lee , Yejin Lee , and Jaehyeong Sim
    In 2024 21st International SoC Design Conference (ISOCC)
  4. SCIE
    Q-LAtte: An Efficient and Versatile LSTM Model for Quantized Attention-Based Time Series Forecasting in Building Energy Applications
    Jieui Kang ,  Jihye Park ,  Soeun Choi , and Jaehyeong Sim
    IEEE Access, vol.12, pp.69325-69341, 2024
    DOI

2023

  1. Optimization of the Modified Gaussian Filter for Mobile GPU Usage in Game Workloads
    Jieui Kang , Jaehyeong Sim, and Hyokyung Bahn
    In 2023 International Conference on Communications, Computing, Cybersecurity, and Informatics (CCCI)
    DOI
  2. TD-NAAS: Template-Based Differentiable Neural Architecture Accelerator Search
    HaYoung Lim , Yeseo Jang , Juyeon Kim , and Jaehyeong Sim
    In 2023 20th International SoC Design Conference (ISOCC)
    DOI

2021

  1. SCIE
    S-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level Sparsity
    Myeonggu Kang , Hyeonuk Kim , Hyein Shin , Jaehyeong Sim, Kyeonghan Kim , and Lee-Sup Kim
    IEEE Transactions on Computers, vol.71, num.6, pp.1291–1304, 2021
    DOI

2020

  1. SCIE
    CREMON: Cryptography Embedded on the Convolutional Neural Network Accelerator
    Yeongjae Choi , Jaehyeong Sim, and Lee-Sup Kim
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol.67, num.12, pp.3337–3341, 2020
    DOI
  2. SCIE
    An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices
    Seungkyu Choi , Jaehyeong Sim, Myeonggu Kang , Yeongjae Choi , Hyeonuk Kim , and Lee-Sup Kim
    IEEE Journal of Solid-State Circuits, vol.55, num.10, pp.2691–2702, 2020
    DOI

2019

  1. Major
    A 47.4 uJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices
    Seungkyu Choi , Jaehyeong Sim, Myeonggu Kang , Yeongjae Choi , Hyeonuk Kim , and Lee-Sup Kim
    In 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC)
    DOI
  2. Top-Tier
    eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators
    Youngbeom Jung , Yeongjae Choi , Jaehyeong Sim, and Lee-Sup Kim
    In 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
    DOI
  3. Top-Tier
    A PVT-Robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks
    Hyein Shin , Jaehyeong Sim, Daewoong Lee , and Lee-Sup Kim
    In 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
    DOI
  4. Top-Tier
    An Energy-Efficient Processing-in-Memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM
    Kyeonghan Kim , Hyein Shin , Jaehyeong Sim, Myeonggu Kang , and Lee-Sup Kim
    In 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
    DOI
  5. Top-Tier
    NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks
    Hyeonuk Kim , Jaehyeong Sim, Yeongjae Choi , and Lee-Sup Kim
    In 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)
    DOI
  6. SCIE
    An Energy-Efficient Deep Convolutional Neural Network Inference Processor with Enhanced Output Stationary Dataflow in 65-nm CMOS
    Jaehyeong Sim, Somin Lee , and Lee-Sup Kim
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.28, num.1, pp.87–100, 2019
    DOI

2018

  1. Top-Tier
    NID: Processing Binary Convolutional Neural Network in Commodity DRAM
    Jaehyeong Sim, Hoseok Seol , and Lee-Sup Kim
    In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
    DOI
  2. Major
    TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training
    Seungkyu Choi , Jaehyeong Sim, Myeonggu Kang , and Lee-Sup Kim
    In 2018 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)
    DOI

2017

  1. SCIE
    Energy-Efficient Design of Processing Element for Convolutional Neural Network
    Yeongjae Choi , Dongmyung Bae , Jaehyeong Sim, Seungkyu Choi , Minhye Kim , and Lee-Sup Kim
    IEEE Transactions on Circuits and Systems II: Express Briefs, vol.64, num.11, pp.1332–1336, 2017
    DOI
  2. Top-Tier
    A Kernel Decomposition Architecture for Binary-Weight Convolutional Neural Networks
    Hyeonuk Kim , Jaehyeong Sim, Yeongjae Choi , and Lee-Sup Kim
    In 2017 IEEE/ACM 54th Annual Design Automation Conference (DAC)
    DOI
  3. Major
    SENIN: An Energy-Efficient Sparse Neuromorphic System with On-Chip Learning
    Myung-Hoon Choi , Seungkyu Choi , Jaehyeong Sim, and Lee-Sup Kim
    In 2017 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)
    DOI

2016

  1. Top-Tier
    A 1.42 TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems
    Jaehyeong Sim, Jun-Seok Park , Minhye Kim , Dongmyung Bae , Yeongjae Choi , and Lee-Sup Kim
    In 2016 IEEE International Solid-State Circuits Conference (ISSCC)
    DOI

2015

  1. SCIE
    A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery with Hybrid Dithering Using a Time-Dithered Ddelta–Sigma Modulator
    Taeho Lee , Yong-Hun Kim , Jaehyeong Sim, Jun-Seok Park , and Lee-Sup Kim
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, num.4, pp.1450–1459, 2015
    DOI

2014

  1. Major
    Timing Error Masking by Exploiting Operand Value Locality in SIMD Architecture
    Jaehyeong Sim, Jun-Seok Park , Seungwook Paek , and Lee-Sup Kim
    In 2014 IEEE 32nd International Conference on Computer Design (ICCD)
    Best Paper Award
    DOI

2013

  1. SCIE
    PowerField: A Probabilistic Approach for Temperature-to-Power Conversion Based on Markov Random Field Theory
    Seungwook Paek , Wongyu Shin , Jaehyeong Sim, and Lee-Sup Kim
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.32, num.10, pp.1509–1519, 2013
    DOI

2012

  1. Top-Tier
    PowerField: A Transient Temperature-to-Power Technique Based on Markov Random Field Theory
    Seungwook Paek , Seok-Hwan Moon , Wongyu Shin , Jaehyeong Sim, and Lee-Sup Kim
    In 2012 IEEE/ACM 49th Annual Design Automation Conference (DAC)
    DOI